5.2 UCS Operation
After a PUC, the UCS module default configuration is:
• XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK.
• DCOCLKDIV is selected for MCLK.
• DCOCLKDIV is selected for SMCLK.
• FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK.
• XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are
configured for XT1 operation.
• When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled.
As previously stated, FLL operation with XT1 is selected by default, but XT1 is disabled. The crystal pins
(XIN, XOUT) are shared with general-purpose I/Os. To enable XT1, the PSEL bits associated with the
crystal pins must be set. When a 32,768 Hz crystal is used for XT1CLK, the fault control logic immediately
causes ACLK to be sourced by the REFOCLK, because XT1 is not stable immediately (see
Section 5.2.12). Once crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to
1.048576 MHz and fDCO = 2.097152 MHz.
Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the MSP430 operating
modes and enable or disable portions of the UCS module (see the SYS chapter). Registers UCSCTL0
through UCSCTL8, configure the UCS module.
The UCS module can be configured or reconfigured by software at any time during program execution.     Once crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to
1.048576 MHz and fDCO = 2.097152 MHz.这句话的意思什么意思？ 是不是说mclk  smclk默认是1.048576MHZ，但是f dco又是什么东西，是不是dco啊？？？难道dco默认是2mhz???     这个是5系类的单片机里面的时钟一部分说明。你们帮我看看啊，谢谢了
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