//三输入异或源文件
module or_3 (x1,x2,x3,z1);
input x1,x2,x3;
output z1;
wire x1,x2,x3;
reg z1;
always @(x1 or x2 or x3)
begin
z1=x1|x2|x3;
end
endmodule

//testbench文件
`timescale 10ns/1ns
module or_3_tb;
reg x1,x2,x3;
wire z1;
initial
begin:apply_stimulus
reg[3:0] i;
for(i=0;i<8;i=i+1)
begin
  {x1,x2,x3}=i [3:0];
  #10 $display ("{x1x2x3} = %b,z1 = %b",{x1,x2,x3},z1);
end
end
or_3 test(
.x1(x1),
.x2(x2),
.x3(x3),
.z1(z1)
);
endmodule

仿真图：


提问：  #10 $display ("{x1x2x3} = %b,z1 = %b",{x1,x2,x3},z1);  这句是不是没起作用，求解！！