verilog 编译错误 Error (10170): Verilog HDL syntax error at..... near text "always"; expecting "end"-黑桃ACE的回答

verilog 编译错误 Error (10170): Verilog HDL syntax error at..... near text "always"; expecting "end"

2019-07-15 22:08发布

module Super_sport
(
   i_clk_50M,
   i_key_left,
   i_key_right,
   i_rst,

   o_led_0,
   o_led_1,
   o_led_2,
   o_led_3,
   o_led_4,
   o_led_5,
   o_led_6,
   o_led_7,
   o_bell

);
//----------------------------------
input i_clk_50M;
input i_key_left;
input i_key_right;
input i_rst;

output o_led_0;
output o_led_1;
output o_led_2;
output o_led_3;
output o_led_4;
output o_led_5;
output o_led_6;
output o_led_7;
output o_bell;

//----------------------------------
reg[25:0] cnt_25M;
reg[25:0] cnt_50M;

reg[7:0] o_led_0;
reg[7:0] o_led_1;
reg[7:0] o_led_2;
reg[7:0] o_led_3;
reg[7:0] o_led_4;
reg[7:0] o_led_5;
reg[7:0] o_led_6;
reg[7:0] o_led_7;
reg[7:0] o_led_8;
reg[7:0] o_led_9;
reg[7:0] o_led_10;
reg[7:0] o_led_11;
reg[7:0] o_led_12;
reg[7:0] o_led_13;
reg[7:0] o_led_14;
reg[7:0] o_led_15;
reg[7:0] o_led_blank;
reg[7:0] o_led_full;

reg drop_blood;
reg game_over;

reg o_bell;

integer second=0;
integer grade=0;
reg quarter;
//---------------------------------时间点
always @ (posedge i_clk_50M or negedge i_rst)//------半秒计时
   begin
   if(!i_rst && cnt_25M==25000000)//其实cnt_25M用25位就可以
      begin
   cnt_25M <= 26'b0;
      grade=1;
   end
   else
      cnt_25M <= cnt_25M + 1'b1;
   end
always @ (posedge i_clk_50M or negedge i_rst)//-------一秒记时
   begin
      if(!i_rst && cnt_50M==50000000)
         begin
cnt_50M<=26'b0;
         second=second+1;
end
      else
         cnt_50M<=cnt_50M+1'b1;
   end
always @ (posedge i_clk_50M)//-----------四分之一秒分频
   begin
      if(cnt_50M[24]==1)
   quarter<=1'b1;
      else
         begin
   cnt_50M<=cnt_50M+1'b1;
         quarter<=1'b0;
   end
   end
//-----------------------------------跑者移动（数码管低电平触发）
always @ (*)
   begin
   if(o_led_0[7]==1&&o_led_0[1]==0&&o_led_0[4]==0&&i_key_left==0)
      begin
   o_led_0[7]<=1;
      o_led_0[1]<=0;
      o_led_0[4]<=0;
   end
   else if(o_led_0[7]==0&&o_led_0[1]==1&&o_led_0[4]==0&&i_key_left==0)
      begin
   o_led_0[7]<=1;
      o_led_0[1]<=0;
      o_led_0[4]<=0;
   end
   else if(o_led_0[7]==0&&o_led_0[0]==0&&o_led_0[4]==1&&i_key_left==0)
      begin
   o_led_0[7]<=0;
      o_led_0[1]<=1;
      o_led_0[4]<=0;
   end
   else
      begin
   o_led_0[7]<=o_led_0[7];
      o_led_0[1]<=o_led_0[1];
      o_led_0[4]<=o_led_0[4];
   end
   end
always @ (*)
   begin
      if(o_led_0[7]==1&&o_led_0[1]==0&&o_led_0[4]==0&&i_key_right==0)
      begin
         o_led_0[7]<=0;
      o_led_0[1]<=1;
      o_led_0[4]<=0;
   end
   else if(o_led_0[7]==0&&o_led_0[1]==0&&o_led_0[4]==0&&i_key_right==0)
      begin
   o_led_0[7]<=0;
      o_led_0[1]<=0;
      o_led_0[4]<=1;
   end
   else if(o_led_0[7]==0&&o_led_0[0]==0&&o_led_0[4]==1&&i_key_right==0)
      begin
   o_led_0[7]<=0;
      o_led_0[1]<=0;
      o_led_0[4]<=1;
   end
   else
      begin
   o_led_0[7]<=o_led_0[7];
      o_led_0[1]<=o_led_0[1];
      o_led_0[4]<=o_led_0[4];
   end
   end
always @ (posedge i_clk_50M)
   begin
        if(game_over==1)
           begin
   o_led_0[7]<=0;
      o_led_0[1]<=0;
      o_led_0[4]<=0;
   end
   else
      begin
      o_led_0[7]<=o_led_0[7];
      o_led_0[1]<=o_led_0[1];
      o_led_0[4]<=o_led_0[4];
   end
   end
//--------------------------------------跑道循环模块
always @ (posedge i_clk_50M or negedge i_rst)
   begin
begin
      o_led_0[7:1]<=7'b0000001;//给跑道赋值
      o_led_1[7:1]<=7'b0100000;
      o_led_2[7:1]<=7'b0000000;
      o_led_3[7:1]<=7'b0010000;
      o_led_4[7:1]<=7'b0100000;
      o_led_5[7:1]<=7'b0000000;
      o_led_6[7:1]<=7'b0010000;
      o_led_7[7:1]<=7'b0000000;
      o_led_8[7:1]<=7'b0100000;
      o_led_9[7:1]<=7'b0000000;
      o_led_10[7:1]<=7'b0010000;
      o_led_11[7:1]<=7'b0000000;
      o_led_12[7:1]<=7'b0100000;
      o_led_13[7:1]<=7'b0000000;
      o_led_14[7:1]<=7'b0010000;
      o_led_15[7:1]<=7'b0000000;
      o_led_blank[7:1]<=7'b0000000;
      o_led_full[7:1]<=7'b1111111;
   end
   begin
   if(!i_rst)
        begin
o_led_0[7:1]<=7'b0000000;
      o_led_1[7:1]<=7'b0000000;
      o_led_2[7:1]<=7'b0000000;
      o_led_3[7:1]<=7'b0000000;
      o_led_4[7:1]<=7'b0000000;
      o_led_5[7:1]<=7'b0000000;
      o_led_6[7:1]<=7'b0000000;
      o_led_7[7:1]<=7'b0000000;
end
   else if(game_over==1)
      begin
o_led_0[7:1]<=o_led_blank[7:1];
      o_led_1[7:1]<=o_led_blank[7:1];
      o_led_2[7:1]<=o_led_blank[7:1];
      o_led_3[7:1]<=o_led_blank[7:1];
      o_led_4[7:1]<=o_led_blank[7:1];
      o_led_5[7:1]<=o_led_blank[7:1];
      o_led_6[7:1]<=o_led_blank[7:1];
      o_led_7[7:1]<=o_led_blank[7:1];
end
      else if(second<=3)
         begin
   o_led_0[7:1]<=o_led_full[7:1];
         o_led_1[7:1]<=o_led_full[7:1];
         o_led_2[7:1]<=o_led_full[7:1];
         o_led_3[7:1]<=o_led_full[7:1];
         o_led_4[7:1]<=o_led_full[7:1];
         o_led_5[7:1]<=o_led_full[7:1];
         o_led_6[7:1]<=o_led_full[7:1];
         o_led_7[7:1]<=o_led_full[7:1];
         o_led_8[7:1]<=o_led_full[7:1];
         o_led_9[7:1]<=o_led_full[7:1];
         o_led_10[7:1]<=o_led_full[7:1];
         o_led_11[7:1]<=o_led_full[7:1];
         o_led_12[7:1]<=o_led_full[7:1];
         o_led_13[7:1]<=o_led_full[7:1];
         o_led_14[7:1]<=o_led_full[7:1];
   o_led_15[7:1]<=o_led_full[7:1];
   end
      else if(second<=5)
         begin
   o_led_0[6:5]<=o_led_blank[6:5];
         o_led_1[6:5]<=o_led_blank[6:5];
         o_led_2[6:5]<=o_led_blank[6:5];
         o_led_3[6:5]<=o_led_3[6:5];
         o_led_4[6:5]<=o_led_4[6:5];
         o_led_5[6:5]<=o_led_5[6:5];
         o_led_6[6:5]<=o_led_6[6:5];
         o_led_7[6:5]<=o_led_7[6:5];
         o_led_8[6:5]<=o_led_8[6:5];
         o_led_9[6:5]<=o_led_9[6:5];
         o_led_10[6:5]<=o_led_10[6:5];
         o_led_11[6:5]<=o_led_11[6:5];
         o_led_12[6:5]<=o_led_12[6:5];
         o_led_13[6:5]<=o_led_13[6:5];
         o_led_14[6:5]<=o_led_14[6:5];
         o_led_15[6:5]<=o_led_15[6:5];
   end
      else if(cnt_25M==25000000)
         begin
   o_led_0[6:5]<=o_led_1[6:5];
         o_led_1[6:5]<=o_led_2[6:5];
         o_led_2[6:5]<=o_led_3[6:5];
         o_led_3[6:5]<=o_led_4[6:5];
         o_led_4[6:5]<=o_led_5[6:5];
         o_led_5[6:5]<=o_led_6[6:5];
         o_led_6[6:5]<=o_led_7[6:5];
         o_led_7[6:5]<=o_led_8[6:5];
         o_led_8[6:5]<=o_led_9[6:5];
         o_led_9[6:5]<=o_led_10[6:5];
         o_led_10[6:5]<=o_led_11[6:5];
         o_led_11[6:5]<=o_led_12[6:5];
         o_led_12[6:5]<=o_led_13[6:5];
         o_led_13[6:5]<=o_led_14[6:5];
         o_led_14[6:5]<=o_led_15[6:5];
         o_led_15[6:5]<=o_led_0[6:5];
      end
      else
         begin
   o_led_0[6:5]<=o_led_0[6:5];
         o_led_1[6:5]<=o_led_1[6:5];
         o_led_2[6:5]<=o_led_2[6:5];
         o_led_3[6:5]<=o_led_3[6:5];
         o_led_4[6:5]<=o_led_4[6:5];
         o_led_5[6:5]<=o_led_5[6:5];
         o_led_6[6:5]<=o_led_6[6:5];
         o_led_7[6:5]<=o_led_7[6:5];
         o_led_8[6:5]<=o_led_8[6:5];
         o_led_9[6:5]<=o_led_9[6:5];
         o_led_10[6:5]<=o_led_10[6:5];
         o_led_11[6:5]<=o_led_11[6:5];
         o_led_12[6:5]<=o_led_12[6:5];
         o_led_13[6:5]<=o_led_13[6:5];
         o_led_14[6:5]<=o_led_14[6:5];
         o_led_15[6:5]<=o_led_15[6:5];
   end
   end
always @ (*)//------game over
begin
   if(!i_rst)
        begin
o_led_0[7:1]<=7'b0000000;
      o_led_1[7:1]<=7'b0000000;
      o_led_2[7:1]<=7'b0000000;
      o_led_3[7:1]<=7'b0000000;
      o_led_4[7:1]<=7'b0000000;
      o_led_5[7:1]<=7'b0000000;
      o_led_6[7:1]<=7'b0000000;
      o_led_7[7:1]<=7'b0000000;
end
   else if(game_over==1)
      begin
o_led_0[7:1]<=o_led_blank[7:1];
      o_led_1[7:1]<=o_led_blank[7:1];
      o_led_2[7:1]<=o_led_blank[7:1];
      o_led_3[7:1]<=o_led_blank[7:1];
      o_led_4[7:1]<=o_led_blank[7:1];
      o_led_5[7:1]<=o_led_blank[7:1];
      o_led_6[7:1]<=o_led_blank[7:1];
      o_led_7[7:1]<=o_led_blank[7:1];
end
   else
      begin
o_led_0[7:1]<=o_led_0[7:1];
      o_led_1[7:1]<=o_led_1[7:1];
      o_led_2[7:1]<=o_led_2[7:1];
      o_led_3[7:1]<=o_led_3[7:1];
      o_led_4[7:1]<=o_led_4[7:1];
      o_led_5[7:1]<=o_led_5[7:1];
      o_led_6[7:1]<=o_led_6[7:1];
      o_led_7[7:1]<=o_led_7[7:1];
end
end
//--------------------------------------血量模块
always @ (*)
   begin
   if(!i_rst)
      begin
o_led_0[0] <= 1'b1;
      o_led_1[0] <= 1'b1;
      o_led_2[0] <= 1'b1;
      o_led_3[0] <= 1'b1;
      o_led_4[0] <= 1'b1;
      o_led_5[0] <= 1'b1;
      o_led_6[0] <= 1'b1;
      o_led_7[0] <= 1'b1;
end
   else if(drop_blood)
   begin
      o_led_0[0]<=1'b1;
      o_led_1[0]<=1'b1;
      o_led_2[0]<=1'b1;
      o_led_3[0]<=1'b1;
      o_led_4[0]<=1'b0;
      o_led_5[0]<=1'b0;
      o_led_6[0]<=1'b0;
      o_led_7[0]<=1'b0;
end
   else
      begin
o_led_0[0]<=o_led_0[0];
      o_led_1[0]<=o_led_1[0];
      o_led_2[0]<=o_led_2[0];
      o_led_3[0]<=o_led_3[0];
      o_led_4[0]<=o_led_4[0];
      o_led_5[0]<=o_led_5[0];
      o_led_6[0]<=o_led_6[0];
      o_led_7[0]<=o_led_7[0];
end
   end
always @ (posedge i_clk_50M)
   begin
        if(game_over==1)
        begin
o_led_0[0]<=1'b0;
      o_led_1[0]<=1'b0;
      o_led_2[0]<=1'b0;
      o_led_3[0]<=1'b0;
      o_led_4[0]<=1'b0;
      o_led_5[0]<=1'b0;
      o_led_6[0]<=1'b0;
      o_led_7[0]<=1'b0;
end
   else
      begin
o_led_0[0]<=o_led_0[0];
      o_led_1[0]<=o_led_1[0];
      o_led_2[0]<=o_led_2[0];
      o_led_3[0]<=o_led_3[0];
      o_led_4[0]<=o_led_4[0];
      o_led_5[0]<=o_led_5[0];
      o_led_6[0]<=o_led_6[0];
      o_led_7[0]<=o_led_7[0];
end
   end
//-------------------------------------裁判模块
always @ (*)
   begin
      if(o_led_0[6]==1)
         begin
   case({o_led_0[1],o_led_0[0],o_led_0[4]})
            3'b100: game_over=1;
            3'b010: drop_blood=1;
            3'b001:
         begin
   game_over=0;
         drop_blood=0;
   end
            default:
         begin
   game_over=0;
   drop_blood=0;
   end
         endcase
   end
      else if(o_led_0[5]==1)
            begin
case({o_led_0[1],o_led_0[0],o_led_0[4]})
                  3'b001: game_over=1;
                  3'b010: drop_blood=1;
                  3'b100:
         begin
   game_over=0;
   drop_blood=0;
   end
                  default:
         begin
   game_over=0;
   drop_blood=0;
   end
            endcase
end
      else
            begin
   game_over=0;
   drop_blood=0;
   end
   end
//-------------------------------------响铃模块

always @ (game_over or second)
   begin
         if(second==1)
   o_bell<=1'b1;
         else if(game_over==1)
         o_bell<=quarter;
         else
         o_bell<=o_bell;
   end
end
//-------------------------------------完结吧
endmodule

报错如下：
Error (10170): Verilog HDL syntax error at Super_sport.v(291) near text "always";  expecting "end"
Error (10170): Verilog HDL syntax error at Super_sport.v(328) near text "always";  expecting "end"
Error (10170): Verilog HDL syntax error at Super_sport.v(364) near text "always";  expecting "end"
Error (10170): Verilog HDL syntax error at Super_sport.v(390) near text "always";  expecting "end"
Error (10170): Verilog HDL syntax error at Super_sport.v(434) near text "always";  expecting "end"
Error (10112): Ignored design unit "Super_sport" at Super_sport.v(1) due to previous errors

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10条回答

黑桃ACE

2019-07-17 05:53

就是楼上说得那里

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